Virtual Memory and Paging

Right now, dozens of processes are running on your computer simultaneously — your browser, your editor, background services. Each one is convinced it has exclusive access to the same enormous block of addresses starting at 0. That cannot all be literally true. And yet it works perfectly.

The trick is virtual memory. Instead of handing each process a slice of real RAM, the operating system gives it a private virtual address space — a fiction the hardware enforces transparently. Every memory address a program uses is a virtual address. Before any byte can actually be read or written, the CPU must silently translate it into a physical address — the real location in RAM chips.

The data structure that records how virtual pages map to physical frames is called a page table. Every process has its own, and it is the cornerstone of memory isolation: even if two processes use the same virtual address, the OS maps them to different physical locations, so neither can ever see the other's data.

Translating every address through a page table would be cripplingly slow, so modern CPUs add a small, fast cache called the Translation Lookaside Buffer (TLB). A TLB hit avoids the table walk entirely; a TLB miss triggers the full lookup and updates the cache. Because programs access memory in clusters — locality of reference — TLB hit rates above 99 % are routine, keeping the overhead nearly invisible.

The demo below shows a tiny system: a 4-bit virtual address space split into 8 pages of 8 bytes each (so a virtual address has a 3-bit page number and a 3-bit offset — but we use 4 bits total here for clarity). A small page table maps virtual page numbers to physical frame numbers, and a two-entry TLB caches the last two translations.

Enter any virtual address (0–63) and press Translate to walk the hardware steps one by one.

<!-- {{c_html_intro}} -->
<div class="container">
  <div class="top-row">
    <div class="input-group">
      <label for="vaddr">{{label_vaddr}}</label>
      <input id="vaddr" type="number" min="0" max="63" value="42" />
      <button id="btnTranslate" type="button">{{btn_translate}}</button>
      <button id="btnReset" type="button" class="ghost">{{btn_reset}}</button>
    </div>
    <div class="legend">
      <span class="badge badge-vpn">{{legend_vpn}}</span>
      <span class="badge badge-off">{{legend_off}}</span>
      <span class="badge badge-pfn">{{legend_pfn}}</span>
    </div>
  </div>
  <div class="panels">
    <div class="panel" id="panelAddr">
      <div class="panel-title">{{panel_addr_title}}</div>
      <div id="addrViz" class="addr-viz"></div>
    </div>
    <div class="panel" id="panelTLB">
      <div class="panel-title">{{panel_tlb_title}}</div>
      <table id="tlbTable" class="mem-table">
        <thead><tr><th>{{th_vpn}}</th><th>{{th_pfn}}</th><th>{{th_valid}}</th></tr></thead>
        <tbody></tbody>
      </table>
    </div>
    <div class="panel" id="panelPT">
      <div class="panel-title">{{panel_pt_title}}</div>
      <table id="ptTable" class="mem-table">
        <thead><tr><th>{{th_vpn}}</th><th>{{th_pfn}}</th><th>{{th_present}}</th></tr></thead>
        <tbody></tbody>
      </table>
    </div>
  </div>
  <div id="log" class="log"></div>
  <div id="result" class="result"></div>
</div>

/* {{c_css_intro}} */
* { box-sizing: border-box; margin: 0; padding: 0; }
body { font-family: system-ui, sans-serif; font-size: 14px; color: #222; }
.container { padding: .6rem .8rem; }
.top-row { display: flex; flex-wrap: wrap; gap: .6rem; align-items: center; margin-bottom: .7rem; }
.input-group { display: flex; flex-wrap: wrap; gap: .4rem; align-items: center; }
label { font-weight: 600; }
input[type=number] { width: 64px; padding: .3rem .4rem; border: 1px solid #adb1b8; border-radius: 6px; font-size: 14px; }
button { font: 600 13px system-ui; padding: .35rem .75rem; border: 1px solid #1d3557; background: #1d3557; color: #fff; border-radius: 6px; cursor: pointer; }
button.ghost { background: #fff; color: #1d3557; }
.legend { display: flex; gap: .4rem; flex-wrap: wrap; align-items: center; }
.badge { display: inline-block; padding: .15rem .5rem; border-radius: 4px; font: 600 12px ui-monospace, monospace; }
.badge-vpn { background: #d4eaff; color: #1d3557; }
.badge-off { background: #fff3cc; color: #7a5700; }
.badge-pfn { background: #d6f5e3; color: #0a5c2a; }
.panels { display: grid; grid-template-columns: 1fr 1fr 1fr; gap: .6rem; margin-bottom: .6rem; }
@media (max-width: 560px) { .panels { grid-template-columns: 1fr; } }
.panel { border: 1px solid #cdd9e3; border-radius: 8px; overflow: hidden; }
.panel-title { background: #e8eef3; padding: .3rem .5rem; font-weight: 700; font-size: 12px; letter-spacing: .03em; }
.mem-table { width: 100%; border-collapse: collapse; font-size: 13px; }
.mem-table th { background: #f0f4f8; padding: .25rem .4rem; text-align: center; font-weight: 700; }
.mem-table td { padding: .25rem .4rem; text-align: center; border-top: 1px solid #e5eaee; font-family: ui-monospace, monospace; }
.mem-table tr.hit td { background: #d6f5e3; }
.mem-table tr.miss td { background: #fde8e8; }
.mem-table tr.fault td { background: #fff3cc; }
.addr-viz { display: flex; gap: 2px; justify-content: center; align-items: center; padding: .5rem .4rem; flex-wrap: wrap; }
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.log .step.warn { color: #b45000; font-weight: 600; }
.log .step.err { color: #c92f3c; font-weight: 600; }
.result { font-weight: 700; font-size: 1.05rem; min-height: 1.5em; }
.result.ok { color: #0a7d33; }
.result.err { color: #c92f3c; }

// Code not found

Notice that a TLB hit resolves in one fast lookup, while a TLB miss requires reading the page table and then updating the TLB. If the page table entry is marked not present, a page fault is raised and the OS would load the page from disk — the moment the illusion of infinite memory becomes concrete.

A flat page table sounds simple, but it hides a painful trade-off.

A 64-bit process could address $2^{64}$ bytes. With a 4 KB page, that means up to $2^{52}$ page-table entries. At 8 bytes per entry, a flat table would need 32 petabytes — for bookkeeping alone, before storing any data. No one can afford that.

The standard solution is a multi-level page table. x86-64 uses four levels (PML4 → PDPT → PD → PT). Each level is only 4 KB, and levels below the root only exist when the corresponding range of addresses is actually used. The space cost shrinks to just the pages that are needed, at the price of up to four memory accesses per translation instead of one.

The TLB is the antidote. Modern CPUs have a two-level TLB hierarchy — a tiny, very fast L1 TLB and a larger, slower L2 TLB — each covering both instruction and data accesses. A context switch between processes must flush (or tag) TLB entries because the new process has a different page table; this flushing cost is a real reason context switches are not free.

Alternative designs tackle the table-size problem differently:

• Inverted page tables keep one entry per physical frame rather than one per virtual page, so the table size is proportional to RAM, not address-space size. Finding an entry requires a hash, adding collision risk.
• Huge pages (2 MB or 1 GB on x86-64) reduce TLB pressure for large allocations like databases and scientific workloads: fewer entries cover the same total memory, dramatically improving hit rates.

Every choice is a negotiation between memory overhead, lookup speed, and the cost of managing the structures when the OS creates, destroys, or migrates processes.

Virtual memory's page-table machinery is the foundation for a surprisingly wide set of OS features:

• Process isolation: each process has its own page table, so a crash or exploit in one process cannot corrupt another's memory. This is the primary reason modern operating systems are stable.
• Memory-mapped files: mapping a file into the virtual address space lets the OS handle file I/O through the same paging mechanism, avoiding separate read/write system calls and enabling efficient sharing between processes.
• Copy-on-write (COW): when a process forks, the child shares the parent's physical frames and both page tables point to the same memory as read-only. Only when either process writes is a private copy made — a key optimization behind fast process creation in Linux and macOS.
• Address Space Layout Randomization (ASLR): the OS maps the stack, heap, and libraries at randomized virtual addresses on every run, making it vastly harder for an attacker to predict where their payload will land.
• Garbage collection: managed-language runtimes exploit write-barrier protection bits in page-table entries to track which memory regions have been modified, enabling generational and incremental GC without scanning all of RAM every cycle.
• Secure enclaves: hardware extensions like Intel SGX use page-table permissions to carve out protected memory regions that even a compromised OS kernel cannot read.

If you want to understand how operating-system scheduling interacts with memory, or why cache behavior matters at the hardware level, page tables are the bridge.

Virtual memory is one of computing's great sleights of hand. Every process runs inside a private fiction — a vast, contiguous address space that belongs to it alone — while the hardware silently maps those virtual addresses to scattered physical frames and the OS shuffles pages to and from disk as needed.

The page table is the ledger that makes the fiction accountable; the TLB is the shortcut that makes it fast; and multi-level structures are the trick that keep the ledger itself from consuming all of RAM. Together they deliver isolation, security, and convenience that programmers rarely have to think about — which is, of course, the whole point.

Peek behind the abstraction once and you will never look at a pointer, a malloc call, or a page-fault message the same way again.